The invention relates to a signal generator and, more particularly, to a control signal generator which is fabricated as a monolithic integrated circuit using a programmable logic array (hereinafter abbreviated to as PLA).
An electronic device such as a memory device, for example, a magnetic bubble memory device or a semiconductor memory device, an information processor or the like, requires control signals providing a series of predetermined logic changes. The control signal of this type is formed by applying parallel output signals from a counter into gate circuits so as to have a given level for each time slot. This method, therefore, needs a number of gate circuits, thus encumbering the minimization of the device. In recent years, a single electronic device needs a number of such control signals. Accordingly, the provision of a number of gate circuits is a serious problem. Recently, an AND-OR type PLA including an AND logic array and an OR logic array or a general purpose PLA including the AND-OR array and an internal feedback loop by flip-flops are preferably used for fabricating a random logic by LSI technology, as disclosed in U.S. Pat. No. 3,566,153. In such a PLA, however, a major part of the regions of the AND or OR arrays, that is to say, storing elements, are not used for a specific purpose so that the use of the array is very inefficient. For example, in a circuit where the parallel output signals from the binary counter are subjected to a programmable logic and flip-flops are driven by the logic outputs, the flip-flops produce timing wave forms, each of which is operable in a proper time slot. Therefore, it is suitable for a timing signal generator. When this is realized by using the general purpose PLA, the internal feedback flip-flops must be used for the respective bits and the output flip-flops of the binary counter, and most of the AND and OR arrays are not used. This is very inefficient.